U.S. Prepares to Establish Its $11 Billion NSTC
The U.S. Department of Commerce, during the first quarter of this year, will issue guidelines on the first proposals for the creation of the $11 billion National Semiconductor Technology Center (NSTC) aimed at restoring the nation’s leadership in the chip industry.
The effort is likened to the collaborative endeavor that created the world’s first nuclear weapons. To take innovation from lab to fab, the NSTC, which is part of the U.S. CHIPS Act, will be a public-private consortium joining government and industry, as well as academia, entrepreneurs, workforce representatives and investors.
“This is a Manhattan Project moment,” Carol Handwerker, a professor of semiconductor materials engineering at Purdue University, told EE Times in an exclusive interview.
The implementation priorities include building domestic manufacturing capacity to reduce reliance on foreign production, Peter Bermel, an associate professor at Purdue, told EE Times in the same interview. He is developing chip radiation-hardening technology in a project funded by the U.S. Department of Defense.
“The vast majority of chip manufacturing is happening abroad, and an even higher percentage of packaging, advanced packaging and heterogeneous integration,” Bermel said.
Several industry organizations, including the American Semiconductor Innovation Coalition (ASIC) and Mitre, have published recommendations on the creation of the NSTC and the National Advanced Packaging Manufacturing Program (NAPMP).
Specialist companies will need to collaborate to provide solutions that are not possible today, Raj Jammy, chief technologist with the Semiconductor Alliance at Mitre Engenuity, told EE Times in an exclusive interview.
“The industry is now being driven more and more by system needs as opposed to saying, ‘Here’s a great next-generation chip, go make some system out of it.’ The situation is reversed now. What it means is that all these solutions that you’re looking for cannot come from one single company.”
Mitre Engenuity and its Semiconductor Alliance have joined U.S. chip companies that account for over half of the domestic industry’s R&D, as well as top American universities.
To avoid duplicating earlier efforts, the NSTC will need to work with overseas groups, such as Belgium’s Interuniversity Microelectronics Centre (imec), which has pioneered key technologies, according to Jammy.
“Having been the driving force behind the innovation in the semiconductor industry for almost 40 years, imec has all of the companies that the U.S. CHIPS Act is trying to support already as partners, thus we are delighted to help and support them (the NSTC) in any way we can,” imec CEO Luc Van den hove said in a statement prepared for EE Times.
“Imec is a great example,” Jammy said. “They have a central facility which has been working on this topic for some time. But in the U.S. now, we have the opportunity to essentially look at this whole problem afresh. We already have facilities on the ground … in Albany Nanotech or in MIT Lincoln Labs. How do we collectively make a network of such facilities so that we can do even bigger things?”
Albany Nanotech, operating the only publicly funded 300-mm chip facility in the U.S., has corporate partners, including IBM, GlobalFoundries, Samsung, Applied Materials, Tokyo Electron, ASML and Lam Research.
“It is absolutely important that we build a resilient network of R&D institutes that we work together with, as well as allied nations,” Jammy said. “There are great capabilities out in Singapore or great capabilities out in France at the Leti Institute. They have some really remarkable work that they have done on SOI-based technologies for power electronics.”
Singapore’s Institute of Microelectronics has “phenomenally good packaging capabilities,” according to Jammy.
The NSTC is also aimed at reducing reliance on China.
“The strategic competition with China is a long game on a complex technology playing field. Securing semiconductor chip manufacturing and ensuring the U.S. and our democratic allies lead the chips of the future is an important way to create resilience against supply chain compromise and denial,” said Laurie Giandomenico, chief acceleration officer at Mitre. “Our role is to help balance industry objectives with national security interests, and that means CHIPS investments must build a sustaining national resource.”
Chip packaging gap
Most of the world’s chip packaging capacity lies outside the U.S.—in China and Taiwan. That’s one of the largest gaps in the U.S. ecosystem. It is possible to reshore the packaging industry through greater automation, Jammy said. Up to now, the high labor intensity of the packaging industry has provided a strong competitive advantage to Asia, where wages are lower.
“A lot of the advanced packaging is now looking more and more like chip fabrication,” Jammy said. “That’s where companies like TSMC [Taiwan Semiconductor Manufacturing Co.] and Intel have excelled. When we introduce automation and new kinds of approaches in making these packages, there is a natural draw toward doing it in the country.”
TSMC and Intel, which have developed 3D packaging technologies, are building new chip facilities in the U.S. in response to the CHIPS Act package of stimulus measures.
As the U.S. prepares to build as many as 13 new chip fabs in the next few years, the NSTC must help solve a shortage of semiconductor engineers and technicians.
Within the next five years, the U.S. will need about 50,000 new semiconductor engineers, more than twice the number that local universities are graduating.
To help fill that gap, the U.S. will probably need to relax visa restrictions to attract semiconductor talent from overseas, the ASIC group said in its recommendations.
“While upcoming efforts by the U.S. government, academia and industry are intended to build a strong domestic pipeline of talent, in the short term, the U.S. industry continues to look to foreign nationals under the H1-B category to supplement the talent pool.”
Even so, the NTSC will need to build more semiconductor talent locally over the long term, according to Jammy.
“There is an opportunity for us to examine very carefully how can we retrain; how can we repurpose people,” he said. “The armed forces, for example, have well trained and well qualified people. With a little bit of training, they could be very useful in fabs. How do we encourage more people, especially minorities and women who have not necessarily had an opportunity?”
Longer term, the U.S. will need to strengthen STEM (science, technology, engineering and math) education to solve human resource shortages, he added.
Management of intellectual property (IP) from a range of companies and organizations will be a problem for the NSTC.
Removing barriers of entry for smaller and medium-sized companies and start-ups, such as the prohibitive cost of IP, is critical to the contribution of these organizations to the semiconductor community, according to a paper published by the ASIC group: “The NSTC should be structured so these entities are able to easily leverage IP to develop new technology and related IP in a way that allows them to license that technology easily and to raise follow-on capital from investors and strategic partners.”
The NSTC project hearkens back to Sematech, a partnership started during the 1980s between the U.S. government and 14 American chipmakers aimed at regaining competitiveness lost to Japan. Sematech helped fund the creation of Albany Nanotech in New York.
“Sematech was set up as an entity which was driven and managed by the chipmakers, but one very important thing that happened was the industry started shifting,” Jammy said, who also served as a VP with Sematech in charge of materials and emerging technologies from 2008 to 2013. “There were many more fabless companies coming into the mix… Today, as we start looking at NSTC and what we need to do, we have to rethink the whole equation, and we have to make sure that all the ecosystem is playing.”
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