TSMC’s Chip Scaling Efforts Reach Crossroads at 2nm
Perpetuating Moore’s Law — the observation that the transistor density in a typical chip doubles every two years — poses a number of challenges at the 3nm node, yet Taiwan Semiconductor Manufacturing Corp. (TSMC) remains optimistic.
There are many predictions Moore’s Law is likely to hit a wall soon, but “how soon?” is open to debate. Also, there are technologies that promise ongoing increases in performance that are not dependent on doubling transistor density. The timing of all that will have far-reaching implications. At last week’s TSMC 2021 Technology Symposium, TSMC CEO C. C. Wei gave the example of data centers, which consume over one percent of global electricity generated.
“Estimates suggest global electricity usage from data centers is projected to grow from five to forty times between 2010 to 2030. Why do projections vary so widely?” Wei asked. “Divergent estimates are partly due to the difficulty of making an accurate projection of our footprint. There are too many variables to consider, including whether Moore’s Law can continue.”
Pessimistic projections are based on the assumption that Moore’s Law is coming to an end, and the efficiency improvements delivered by semiconductor process technologies can no longer keep up with demand for data and computing power, he noted.
As TSMC’s silicon shrink roadmap appears to end at the 2nm node, the world’s largest semiconductor foundry is turning to a combination of technologies in packaging and new materials to stay on the path of increasing transistor density to boost processing while lowering power demand.
“We have a predictable and reliable roadmap for both 2D scaling and 3D ICs to pursue more Moore and beyond Moore,” Wei said. “We continue to offer the most advanced logic technology to prove 2D scaling is alive and kicking.”
The company said that at this point, there’s no plan for process nodes beyond 2nm. At the technology symposium, TSMC offered a few details on the company’s first 2nm fab, which will be built in Hsinchu, Taiwan. Outside of providing details on the fab site, the company didn’t elaborate on a timeframe for production or capacity.
The shift in process technology to packaging and new materials is expected to fundamentally change chip production.
“The industry continues to find new ways to innovate as Moore’s Law slows,” Brett Simpson, a senior analyst with Arete Research, told EE Times. “The adoption of advanced packaging creates a new paradigm for the semis industry, where chipmakers and foundries are clearly adding more value — rather than selling silicon, increasingly the industry is going to sell platforms. We think this is a critical development in compute at a time when big monolithic chips are no longer meeting the needs of customers.”
Last year, TSMC combined its wafer-level 3D IC platforms under one umbrella called 3DFabric, including both frontend and backend technologies as well as TSMC’s latest offering, SoIC (system on integrated chips) for silicon stacking. TSMC has multiple backend fabs that assemble and test silicon dies, including 3D stacks, into packaged devices. 3DFabric includes the company’s older CoWoS and InFO packaging technologies.
“Recent discussions at Semicon Taiwan and other events we’ve been able to attend have pointed to 3DFabric as a key piece to keep enabling power/performance/system level improvements through the next decade as traditional scaling gets more technically complicated and expensive,” Credit Suisse analyst Randy Abrams told EE Times.
By 2022, Wei said SoIC will be ready for volume production, and by the end of the same year, the company will have a total of five dedicated fabs for 3DFabric.
One key technology shift will be from FinFET devices to new gate-all-around FETs (GAA FETs) at the 3nm or 2nm nodes. GAA provides better performance, but the transition could be difficult. TSMC rival Samsung may lead TSMC with the move to nanosheet GAA at the 3nm node, possibly as early as next year.
“What is clear from the shift to nanofilm is that the manufacturing challenges are going to be really challenging, capital intensity is rising, and not everyone is going to be successful. With gate-all -around transistors, the industry has to up their game,” according to Simpson.
TSMC said it will probably not introduce gate all around until after the 3nm node.
“Going forward, beyond FinFET, nanosheet transistors could offer additional performance and power efficiency,” TSMC R&D SVP Y.J. Mii said in a presentation at the symposium. TSMC has been working on nanosheet transistors for more than 15 years he said.
One of the key advantages of a nanosheet device is its short channel control, which is critical to threshold voltage variation, Mii said. Smaller vt variation is critical to achieving good performance and lower voltage.
“We have demonstrated nanosheet transistors with more than 50 percent lower vt variations,” Mii said. “As scaling continues, design and technology co-optimization (DTCO) will provide further benefits. We have built a solid DTCO capability. Nanosheets have opened up several new opportunities to use DTCO to boost performance.”
It is extremely challenging to generate multiple vt for nanosheet devices due to limited-sheet-to-sheet space, according to Mii. With innovative materials and process flow, TSMC has demonstrated up to 12 vt options with a wide range of vt coverage for customers’ consideration of power and performance optimization, he added.
Some of TSMC’s largest customers, including Advanced Micro Devices (AMD), said they are on board with DCTO.
“As we look forward to 5nm and beyond, the challenges of designing competitive products that meet our rigorous targets for performance, power and yield will continue to grow,” said AMD CEO Lisa Su in a presentation at the symposium. “Accomplishing this will require a partnership that is not only deep on design and technological optimization, but also one that has the breadth to innovate across multiple markets and across both fab and packaging technologies. We’re also very excited about TSMC’s leading packaging technology, which enables us to architect our products in a very creative way.
TSMC said innovations beyond 3nm include novel transistor structures, new materials, and new conductor materials.
The company claimed a backend interconnect breakthrough with a novel annealing process that increases copper grain size by more than seven times compared to the conventional process. The process will reduce line resistance by 30 percent and increase the extent of interconnect scaling, according to TSMC.
TSMC is also expanding its InFO offerings. TSMC said it expects to qualify InFO B for smartphone applications in the second half of 2021. An Info B package can be less than 450 microns thick and house a mobile SoC, with size up to 135 millimeters square. The company said it has a 14mm-by-14mm InFO package to meet the most stringent form factor requirements.
TSMC is developing InFO OS, or InFO on substrate technology, for HPC applications as well as CoWoS R and CoWoS L to satisfy various customers needs.
For 3D chip stacking, TSMC has been developing chip-on-wafer and wafer-on-wafer technologies for applications such as high-performance computing (HPC) applications. TSMC plans to qualify 7nm on 7nm chip-on-wafer technology by the end of 2021 and 5nm on 5nm in 2022. The company is targeting wafer-on-wafer technology for logic on deep trench capacitor integration.
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