The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration
As demand for high-performance semiconductors increases, the semiconductor market is paying more attention to the importance of the “packaging process”. In line with this trend, SK hynix is mass-producing advanced packaging products based on HBM3 (High Bandwidth Memory 3) while focusing on investing in production lines and securing resources for the development of future packaging technologies. Some businesses that have previously focused on technology for semiconductor memory manufacturing are investing more in packaging technology than OSAT1 companies that specialize in such technology. This trend is driven by the belief that packaging technology will strengthen the competitiveness of the semiconductor industry and the companies within it.
1OSAT (Outsourced Semiconductor Assembly and Test): A company that specializes in semiconductor packaging and testing.
This article will provide an accessible overview of packaging technology, which has been considered a difficult topic for the general public to approach due to its complexity. The meaning, role, and evolution of packaging technology will be examined, followed by a look into the development of SK hynix’s packaging technology that has led to the current focus on heterogeneous integration. Finally, the direction of the company’s future technological developments will be introduced.
The Meaning and Role of Packaging Technology
First, let’s look at the four main functions of the packaging process. The first and most basic purpose is to protect the semiconductor chip from external shock or damage. The second is to transmit external power to the chip for its operation, and the third is to provide wiring for the chip to perform the input and output of electrical signals during operation. The last role is to properly distribute the heat generated by the chip to ensure stable operation. Recently, the function of heat dissipation, or heat distribution, has become increasingly important.
The role of packaging can be seen in Figure 1. For example, there is a significant gap between the scale required by the system and the scale provided by CMOS2, but they can be connected through packaging technology. Similarly, there is a gap between the density required by the system and the density that CMOS can provide. This issue can be resolved through the packaging process as it helps increase the density of the CMOS. In other words, packaging technology acts as a bridge between semiconductor devices and systems. The importance of this connection method, therefore, increases gradually.
2CMOS (Complementary Metal Oxide Semiconductor): An integrated circuit design on a printed circuit board (PCB) that uses semiconductor technology.
Three Stages of Packaging Development: Stack Competition, Performance Competition, and Convergence
When examining the history of packaging technology, it can be divided into three major eras. In the past, a single package would only implement one chip. Consequently, packages were simple and had no distinguishing factors, and the value added by packaging technology was low. However, in the early 2000s, with the switch to FBGA3 packaging, the stacking of multiple chips on one package began. This can be referred to as the “Era of Stacking Competitiveness.” As chips began to be stacked, the form of the package diversified and various derivative products were created depending on the combination of the memory chips. The MCP4, which implements DRAM and NAND in the same package, also appeared at this time.
3FBGA (Fine Pitch Ball Grid Array): A type of surface-mount packaging (a chip carrier) used for integrated circuits based on ball grid array technology. It has thinner contacts and is mainly used in system-on-a-chip designs.
4MCP (Multi Chip Package): A product made into a single package by vertically stacking two or more different types of memory semiconductors.
The second era began after 2010 when a method of interconnection using a bump on a chip appeared. As a result, changes in the operating speed and the device property margins occurred. This period can be called the “Era of Performance Competitiveness” as packaging technology prior to 2010 generally involved connecting metal wires, but the introduction of bumps shortened the signal path to achieve faster speeds. Meanwhile, the stacking method using TSV5 drastically increases the number of I/Os (Input/Output), which leads to connecting 1,0246 wide I/Os enabling high operating speeds even in low voltage. In this era of performance competitiveness, the properties of chips change according to the packaging technology, and this becomes an important factor in fulfilling the requirements of the customers. As the success or failure of a business can depend on the presence or absence of packaging technology, the value of packaging technology has continued to grow.
The third and final era began in 2020 and is based on all the previous packaging technologies. It can be considered the “Convergence Era” as it requires technology that can connect various types of chips into one package and, also, connect many parts into one module when incorporating a system. In this era, packaging technology itself can become a system solution, and customized packaging solutions can be provided to customers to make small quantity batch production possible. At this point, merely owning packaging technology will determine the success of a business.
5TSV (Through-Silicon Via): Interconnection technology that drills thousands of fine holes in DRAM chips and connects the holes of the upper and lower layers with electrodes that penetrate vertically.
61,024: Standard DRAM has up to 64 I/Os, whereas HBM3 has a maximum of 1,024 wide I/Os.
History of SK hynix’s Packaging Technology
SK hynix’s packaging technology underwent significant development throughout the aforementioned eras. Although the company‘s packaging technology was not significantly differentiated up to the stacking competitiveness era, as the performance competitiveness era began, SK hynix became renowned for its packaging technology. In particular, CoC7 technology, which combines bump interconnection and wire bonding, ushered in innovation that includes faster speeds and reduced costs. It is currently a specialized technology applied in the production and manufacturing of SK hynix’s high density modules. Additionally, SK hynix has developed MR-MUF8 technology and has been applying it to HBM products. This technology improves the quality in more than 100,000 micro bump interconnections of HBM. In addition, this packaging technology has sufficiently increased the number of thermal dummy bumps while excelling in heat dissipation compared to its competitors as it applies a molded underfill (MUF) material which has high thermal conductivity. This advancement has helped SK hynix increase its share of the HBM market and eventually take a leading position in the HBM3 sector.
7CoC (Chip-on-Chip): A packaging technology designed to electrically connect two (or more) dies together without the need for TSV (Through-Silicon Via).
8MR-MUF (Mass Reflow Molded Underfill): MR-MUF refers to the process of attaching semiconductor chips to circuits and filling the space between chips and the bump gap with a material called ‘liquid EMC’ (Epoxy Molding Compound) when stacking up chips. So far, NCF technology has been used for this process. NCF is a method of stacking chips by using a kind of film between chips. The MR-MUF method has about twice the thermal conductivity compared to NCF and affects the process speed as well as the yield.
Today, in the convergence era, SK hynix is promoting the development of Hybrid Bonding technology which uses Cu–to–Cu bonding9 instead of soldering. Moreover, the company is reviewing multiple options for applying various packaging technologies including grafting the Fan-out RDL10 technology. Hybrid Bonding technology allows for finer pitches11 and, accordingly, has the advantage in terms of the height of the packaging as it is a gapless bonding technique that does not use solder bumps when stacking chips. In addition, Fan-out RDL technology is applicable to various platforms, so SK hynix plans to use it when incorporating packages with Chiplet12. Line pitch and multi-layer are key components of Fan-out technology, and SK hynix aims to secure RDL technology below 1 micron, or at sub-micron level, by 2025.
9Cu-to-Cu (Copper-to-Copper) Bonding: One of the hybrid bonding methods of the packaging process, which provides a solution for 10µm pitches and below by completely avoiding the use of bumps. Direct copper-to-copper connections are applied in this process when dies in packages need to be connected to each other.
10RDL (Redistribution Layer): An extra metal layer on an integrated circuit that reroutes its I/O pads in other desired locations of the chip, for better access to the pads where necessary. For example, a bump array located in the center of a chip can be redistributed to positions near the chip edge. The ability to redistribute points can enable higher contact density and enable subsequent packaging steps.
11Pitch: Minimum center-to-center distance between interconnect lines
12Chiplet: Technology that divides chips by use such as controller or high-speed memory, and manufactures them as separate wafers before re-connecting them in the packaging process
Packaging technology will become an important means of providing holistic system solutions that go beyond one-dimensional functions such as chip protection and supplying power. It won’t be long before companies will need to possess packaging technology to become a leader in the semiconductor industry. Several years ago, a major foundry company in East Asia not only created a new system-in-package (SiP) business through a technology called integrated fan-out (InFO) packaging, but it was also able to increase the existing business area of foundry sales—which has great implications for SK hynix. Just as this company is known for its production of controllers, SK hynix is renowned for producing high-performance semiconductor memories such as its HBM. SK hynix also developed advanced packaging technologies such as heterogenous integration and fan-out RDL technology—key packaging technologies in the upcoming convergence era. Consequently, the company is not only playing a role as a memory-integrated device manufacturer (IDM) but is also becoming a total “solution provider” that can lead the future semiconductor memory industry.
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