Avery Introduces Chiplet Verification IP
With the recent formalization of a chiplet standard, it was inevitable that verification IP support would follow.
Avery Design Systems, known for its functional verification solutions for key semiconductor technologies, including PCI Express (PCIe), Compute Express Link (CXL), and HMB3, now offers comprehensive support for the new Universal Chiplet Interconnect Express (UCIe) with high–quality models and test suites that support pre–silicon verification of systems using UCIe.
The die–to–die interface standard was announced earlier this year and is guided by a consortium of members that includes Avery as well as founding members Intel, AMD, Arm, Qualcomm, TSMC, Samsung, ASE, Google, Microsoft, and Meta — among others. The standard supports interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
The first iteration of the UCIe standard covers the UCIe Adapter and PHY, including die–to–die I/O physical layer, die–to–die protocols, and a software stack that leverages the well–established PCIe and CXL industry standards in addition to a protocol–agnostic raw transfer mode.
Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre–silicon validation of design elements. Its UCIe offering supports standalone UCIe die–to–die adapter and LogPHY verification, along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models, the company provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test suites utilizing a flexible and open architecture.
Chiplets are not new — major semiconductor manufacturers have turned to chiplets to counter the physical limitations of Moore’s Law. Companies designing systems around chiplets had to conduct tests and verify their designs, but before the standard was formalized, Avery encountered customers who were using die–to–die interfaces that were somewhat proprietary in nature.
“It was good for closed systems were using their own IP on both dies. However, the benefit of having a standard allows you more interoperability, more trust, and more confidence in interoperability between dies coming from different vendors,” said Chris Browy, VP of sales and marketing at Avery.
Having both a standard and a verification IP reduces risk, he said, and provides more customers confidence in pursuing chip–based designs. Avery observed increased interest from IP companies that wanted a die–to–die interface standard leading up the introduction of the UCIe. As a result, the company looked to cover as many scenarios as possible. “We never know what customers are going to do.”
Browy said developing a verification IP is easier than developing an IP. “We only address the digital level. We don’t get into analog behavior.” In the meantime, it’s a new standard that will take time to mature, and other protocols will likely be added to the VIP over time. “The more verification they can do early on, the better.”
— Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.
The post Avery Introduces Chiplet Verification IP appeared first on EETimes.